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參數資料
| 型號： | 70T631S12DDGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144 |
| 文件頁數： | 1/27頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 70T631S12DDGI |
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2009 Integrated Device Technology, Inc.
1
JANUARY 2009
DSC-5670/6
Functional Block Diagram
◆
Full hardware support of semaphore signaling between
ports on-chip
◆
On-chip port arbitration logic
◆
Fully asynchronous operation from either port
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
Sleep Mode Inputs on both ports
◆
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
◆
Single 2.5V (±100mV) power supply for core
◆
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆
RapidWrite Mode simplifies high-speed consecutive write
cycles
◆
Dual chip enables allow for depth expansion without
external logic
◆
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
◆
M/
S = VIH for BUSY output flag on Master,
M/
S = VIL for BUSY input on Slave
◆
Busy and Interrupt Flags
HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
IDT70T633/1S
1. Address A18x is a NC for IDT70T631.
2.
BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
CE0R
R/
WR
CE1R
LBR
UBR
512/256K x 18
MEMORY
ARRAY
Address
Decoder
A18R(1)
A0R
Address
Decoder
CE0L
R/WL
CE1L
LBL
UBL
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
I/O0L-I/O17L
I/O0R -I/O17R
Din_L
ADDR_L
Din_R
ADDR_R
OER
OEL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/
S
R/
WL
OEL
R/
WR
OER
CE0L
CE1L
CE0R
CE1R
5670 drw 01
A18L(1)
A0L
ZZ
CONTROL
LOGIC
ZZL
(4)
ZZR
(4)
JTAG
TCK
TRST
TMS
TDI
TDO
INTL(3)
SEML
BUSYL(2,3)
BUSYR(2,3)
SEMR
INTR(3)
NOTES:
◆
Green parts available, see ordering information
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相關代理商/技術參數 |
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| 70T631S15BC | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 2.5V 4M-Bit 256K x 18 15ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 2.5V 4.5MBIT 256KX18 15NS 256BGA - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:256K X 18 STD-PWR, 2.5V DUAL PORT RAM |
| 70T631S15BC8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 2.5V 4M-Bit 256K x 18 15ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 2.5V 4.5MBIT 256KX18 15NS 256BGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256K X 18 STD-PWR, 2.5V DUAL PORT RAM |
| 70T631S15BF | 功能描述:靜態隨機存取存儲器 256K X 18 STD-PWR, 2.5V DUAL PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70T631S15BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 2.5V 4M-Bit 256K x 18 15ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 2.5V 4.5MBIT 256KX18 15NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256K X 18 STD-PWR, 2.5V DUAL PORT RAM |
| 70T633S10BC | 功能描述:靜態隨機存取存儲器 512K X 18 STD-PWR, 2.5V DUAL PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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