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參數資料
| 型號： | 71M6531D-IMR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數： | 69/120頁 |
| 文件大?。?/td> | 2477K |
| 代理商： | 71M6531D-IMR/F |
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
52
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
V3P3
V3P3 -
400mV
V3P3 - 10mV
VBIAS
0V
Battery
modes
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
1.5.16 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included
in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as
its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part
is reset as if the RESET pin were pulled high, except that the I/O RAM bits
will be in the same state as after a wake-up from SLEEP or LCD modes
(see the I/O RAM description in Section 4.2 for a list of I/O RAM bit states
after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the
WDT overflow, the MPU will be launched from program address 0x0000.
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT.
Figure 17: Functions defined by V1
The WDT can be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this also deactivates
V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the
WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part
will be reset to a known state.
Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT
mode. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The
watchdog timer is also reset when the internal signal WAKE = 0 (see Section 2.5 Wake-Up Behavior).
If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets
the chip. This can be used to determine the cause of a WDT reset since it allows the code to log its state
(e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.
相關PDF資料 |
PDF描述 |
|---|---|
| 71M6532D-IGTR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 71M6532F-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 71M6531D-IM/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 71M6531F-IMR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 71M6531F-IM/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 71M6531F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC |
| 71M6531F-DB | 功能描述:開發板和工具包 - 8051 71M6531F Demo Brd RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 71M6531F-IM/F | 功能描述:計量片上系統 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6531F-IM/F3 | 功能描述:計量片上系統 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6531F-IM/F4 | 功能描述:計量片上系統 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
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