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參數資料
型號： 71M6533-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數： 105/124頁
文件大小： 2008K
代理商： 71M6533-IGT/F
FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
81
FIR_LEN[1:0]
2007[3:2]
1
R/W
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter.
[M40MHZ, M26MHZ]
FIR_LEN
Resulting FIR
Filter Cycles
Resulting
ADC Gain
[00], [10], or [11]
00
138
0.110017
01
288
1.000
10
384
2.37037
[01]
00
186
0.113644
01
384
1.000
10
588
3.590363
FL_BANK[1:0]
FL_BANK[2:0]*
SFR B6[1:0]
SFR B6[2:0]
1
R/W
Flash bank selection register. Flash memory above 32 k is mapped to the MPU ad-
dress space from 0x8000 to 0xFFFF in 32 k banks. When MPU address[15] = 1, the
address in flash is mapped to FL_BANK[1:0] or FL_BANK[2:0], MPU Address[14:0].
FL_BANK is reset by the erase cycle.
FLSH_ERASE
[7:0]
SFR 94[7:0]
0
W
Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE.
FLSH_MEEN
SFR B2[1]
0
W
Mass Erase Enable.
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR
[5:0]
SFR B7 [7:2]
0
W
Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR[5:0] with FL_BANK[2:0], sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
FLSH_PWE
SFR B2[0]
0
R/W
Program Write Enable. This bit must be cleared by the MPU after each byte write op-
eration. Writes to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
FOVRIDE
20FD[4]
0
R/W
Permits the values written by the MPU to temporarily override the values in the fuse
register (reserved for production test).
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相關代理商/技術參數
參數描述
71M6533-IGTR/F 功能描述:計量片上系統 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
71M6533-IGTR/F1 功能描述:計量片上系統 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
71M6533-IGTR/F2 功能描述:計量片上系統 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
71M6534 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC
71M6534H 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC
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