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參數資料
型號： 71M6542F-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數： 75/165頁
文件大小： 2208K
代理商： 71M6542F-IGT/F
v1.1
2008–2011 Teridian Semiconductor Corporation
17
For both multiplexer sequences shown in Figure 6 and Figure 7, the frame duration is 13 CK32 cycles
(where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.
Table 3 summarizes the various AFE input configurations.
CK32
MUX STATE
0
1
2
MUX_DIV[3:0] = 3 Conversions
Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
0
S
11/5/2010
Fig. 2:
IA
VA
IB
Fig. 3:
IA
VA
Not Used
Fig. 5:
IA
VA
VB
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3)
CK32
MUX STATE
0
1
2
3
MUX_DIV = 4 Conversions
Settle
Multiplexer Frame
S
CROSS
MUX_SYNC
0
S
11/5/2010
Fig. 4:
IA
VA
IB
VB
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4)
Table 3: ADC Input Configuration
Pin
ADC
Channel
Required
Setting
Comment
IAP
ADC0
DIFFA_E = 1
Differential mode must be selected with DIFFA_E = 1 (I/O
RAM 0x210C[4]). The ADC results are stored in CE RAM
location ADC0 (CE RAM 0x0), and ADC1 (CE RAM 0x1) is not
disturbed.
IAN
ADC1
IBP
ADC2
DIFFB_E = 1
or
RMT_E = 1
For locally connected sensors (Figure 2 and Figure 4), the
differential input must be enabled by setting DIFFB_E (I/O
RAM 0x210C[5].
For the remote connected sensor (Figure 3 and Figure 5)
with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3])
must be set.
In both cases, the ADC results are stored in RAM location
ADC2 (CE RAM 0x2), and ADC3 (CE RAM 0x3) is not
disturbed.
IBN
ADC3
VA
ADC10
--
Single-ended mode only. The ADC result is stored in RAM
location ADC10 (CE RAM 0xA).
VB
ADC9
--
Single-ended mode only (71M6542F only). The ADC result
is stored in RAM location ADC9 (CE RAM 0x9).
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,
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