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參數資料
| 型號： | 71M6542G-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數： | 101/165頁 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGTR/F |
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2008–2011 Teridian Semiconductor Corporation
v1.1
Table 24: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol Function
Timer/Counter 1
TMOD[7]
Gate
If TMOD[7] is set, external input signal control is enabled for Counter 1. The
TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1 to
increment. With these settings, Counter 1 increments on every falling edge of the
logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the
contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is performed.
When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4]
M1:M0
Selects the mode for Timer/Counter 1, as shown in Table 22.
Timer/Counter 0:
TMOD[3]
Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to
increment. With these settings, Counter 0 is incremented on every falling edge of
the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by
the contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
TMOD[2]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a timer.
TMOD[1:0]
M1:M0
Selects the mode for Timer/Counter 0 as shown in Table 22.
Table 25: The TCON Register Bit Functions (SFR 0x88)
Bit
Symbol Function
TCON[7]
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TCON[6]
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TCON[5]
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is processed.
TCON[4]
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON[3]
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is
observed. Cleared when an interrupt is processed.
TCON[2]
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input pin
to cause an interrupt.
TCON[1]
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is
observed. Cleared when an interrupt is processed.
TCON[0]
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input pin
to cause interrupt.
2.4.7
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.4.8
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own
interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by
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