- 您現在的位置：買賣IC網 > PDF目錄294101 > 71V2556XSA166BGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 128K X 36 ZBT SRAM, PBGA119 PDF資料下載
參數資料
| 型號： | 71V2556XSA166BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, PBGA119 |
| 封裝： | GREEN, BGA-119 |
| 文件頁數： | 1/23頁 |
| 文件大小： | 350K |
| 代理商： | 71V2556XSA166BGI8 |
APRIL 2011
DSC-4875/12
1
2011IntegratedDeviceTechnology,Inc.
Pin Description Summary
Description
The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Features
◆
◆ 128K x 36 memory configurations
◆
◆ Supports high performance system speed - 166 MHz
(3.5 ns Clock-to-Data Access)
◆
◆ ZBTTM Feature - No dead cycles between write and read
cycles
◆
◆ Internally synchronized output buffer enable eliminates the
need to control OE
◆
◆ Single R/W (READ/WRITE) control pin
◆
◆ Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆
◆ 4-word burst capability (interleaved or linear)
◆
◆ Individual byte write (BW1 - BW4) control (May tie active)
◆
◆ Three chip enables for simple depth expansion
◆
◆ 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
◆
◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
◆
◆ Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP) and 119 ball grid array (BGA)
A0 A
- 6
1
s
t
u
p
n
I
s
e
r
d
At
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
E
C 1
E
C
,
2
,
E
C 2
s
e
l
b
a
n
E
p
i
h
Ct
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
E
O
e
l
b
a
n
E
t
u
p
t
u
Ot
u
p
n
Is
u
o
n
o
r
h
c
n
y
s
A
/
R
W
l
a
n
g
i
S
e
ti
r
W
/
d
a
e
Rt
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
N
E
C
e
l
b
a
n
E
k
c
o
l
Ct
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
W
B 1, W
B 2, W
B 3, W
B 4
s
t
c
e
l
e
S
e
ti
r
W
e
t
y
B
l
a
u
d
i
v
i
d
n
It
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
K
L
Ck
c
o
l
Ct
u
p
n
IA
/
N
/
V
D
A
D
L
s
e
r
d
a
w
e
n
d
a
o
L
/
s
e
r
d
a
t
s
r
u
b
e
c
n
a
v
d
At
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
O
B
L
r
e
d
r
O
t
s
r
u
B
d
e
v
a
e
lr
e
t
n
I
/
r
a
e
n
i
Lt
u
p
n
Ic
it
a
t
S
M
Tt
c
e
l
e
S
e
d
o
M
t
s
e
Tt
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
I
D
Tt
u
p
n
I
a
t
a
D
t
s
e
Tt
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
K
C
Tk
c
o
l
C
t
s
e
Tt
u
p
n
IA
/
N
O
D
Tt
u
p
t
u
O
a
t
a
D
t
s
e
Tt
u
p
t
u
Os
u
o
n
o
r
h
c
n
y
S
T
S
R
T
)l
a
n
o
it
p
O
(
t
e
s
e
R
G
A
T
Jt
u
p
n
Is
u
o
n
o
r
h
c
n
y
s
A
Z
Ze
d
o
M
p
e
l
St
u
p
n
Is
u
o
n
o
r
h
c
n
y
S
O
/I 0 O
/I
-
1
3
O
/I
,
1
P
O
/I
-
4
P
t
u
p
t
u
O
/
t
u
p
n
I
a
t
a
DO
/Is
u
o
n
o
r
h
c
n
y
S
V D
D
V
,
Q
D
r
e
w
o
P
O
/I
,r
e
w
o
P
e
r
o
Cy
l
p
u
Sc
it
a
t
S
V S
S
d
n
u
o
r
Gy
l
p
u
Sc
it
a
t
S
1
0
l
b
t
5
7
8
4
IDT71V2556S/XS
IDT71V2556SA/XSA
128K x 36
3.3V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556 contains data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71V2556tobe
suspended as long as necessary. All synchronous inputs are ignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1,CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
TheIDT71V2556hasanon-chipburstcounter.Intheburstmode,the
IDT71V2556 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBO
inputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
TheIDT71V2556SRAMsutilizeIDT's latesthigh-performanceCMOS
processandarepackagedinaJEDECstandard14mmx20mm100-pin
thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).
相關PDF資料 |
PDF描述 |
|---|---|
| 71V2556S100PFG8 | 128K X 36 ZBT SRAM, 5 ns, PQFP100 |
| 71V65703S85BQ | 256K X 36 ZBT SRAM, 8.5 ns, PBGA165 |
| 7204G1 | 2 CONTACT(S), MALE, POWER CONNECTOR, SOLDER, PLUG |
| 7204G3 | 2 CONTACT(S), MALE, POWER CONNECTOR, SOLDER, PLUG |
| 7204 | 2 CONTACT(S), MALE, POWER CONNECTOR, SOLDER, PLUG |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 71V256S10YG | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 256KBIT 32KX8 10NS 28PIN SOJ - Rail/Tube |
| 71V256S10YG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 256KBIT 32KX8 10NS 28PIN SOJ - Tape and Reel |
| 71V256S12YG | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 256KBIT 32KX8 12NS 28PIN SOJ - Rail/Tube |
| 71V256S12YG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 256KBIT 32KX8 12NS 28PIN SOJ - Tape and Reel |
| 71V256SA10PZ | 制造商:Integrated Device Technology Inc 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。