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參數(shù)資料
| 型號： | 71V35781S183PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 632K |
| 代理商： | 71V35781S183PF |
MARCH
2009
DSC-5301/03
1
2003 Integrated Device Technology, Inc.
Features
◆
◆ 128K x 36, 256K x 18 memory configurations
◆
◆ Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
◆
LBO input selects interleaved or linear burst mode
◆
◆ Self-timed write cycle with global write control (
GW),bytewrite
enable (
BWE), and byte writes (BWx)
◆
◆ 3.3V core power supply
◆
◆ Power down controlled by ZZ input
◆
◆ 3.3V I/O
◆
◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆
◆ Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Description
The IDT71V35761/781 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(
ADV=LOW),thesubsequentthreecyclesofoutput
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO input pin.
The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
Pin Description Summary
NOTE:
1.
BW3 and BW4 are not applicable for the IDT71V35781.
A0-A17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0,
CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
5301 tbl 01
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
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