
1
CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
JANUARY 2009
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3208/8
FEATURES:
The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs
The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs
The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs
The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs
The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs
The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs
Low power consumption
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
Ultra high speed—12 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bi-directional, width expansion, depth expansion,
bus-matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS technology
Space-saving TSSOP
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional
andcompatibletotwoIDT7200/7201/7202/7203/7204/7205FIFOsinasingle
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth
word size and depth.
Thereadsandwritesareinternallysequentialthroughtheuseofringpointers,
with no address information required to load and unload data. Data is toggled
in and out of the devices through the use of the Write (
W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
errorchecking.ItalsofeaturesaRetransmit(
RT)capabilitythatallowsforreset
of the read pointer to its initial position when
RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA
WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSA
FLA/RTA
XOA/HFA
FFA
EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
RAM
ARRAY B
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSB
FLB/RTB
3208 drw 01
XOB/HFB
FFB
EFB
(DA0-DA8)
(DB0-DB8)
(QB0-QB8)
(QA0-QA8)
RAM
ARRAY A
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9