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參數資料
| 型號： | 72V3684L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數： | 1/36頁 |
| 文件大小： | 418K |
| 代理商： | 72V3684L15PF |
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IDT72V3684
IDT72V3694
IDT72V36104
3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
1
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4677/6
NOVEMBER 2003
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Memory storage capacity:
IDT72V3684
–
16,384 x 36 x 2
IDT72V3694
–
32,768 x 36 x 2
IDT72V36104 –
65,536 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Retransmit Capability
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644/72V3654/72V3664/72V3674
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
16
EFB/ORB
AEB
36
FFB/IRB
AFB
B0-B35
FFA/IRA
AFA
FS2
FS0/SD
FS1/
SEN
A0-A35
EFA/ORA
AEA
4677 drw01
36
Output
Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
36
Input
Bus-
Matching
FIFO1 and
FIFO2
Retransmit
Logic
RT1
RT2
RTM
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 72V3690L10PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L10PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L15PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PFI | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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