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參數資料
| 型號： | 73M1903-IGV |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數： | 37/45頁 |
| 文件大?。?/td> | 449K |
| 代理商： | 73M1903-IGV |
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73M1903
Modem Analog Front End
DATA SHEET
ge: 42 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 1.4
Example 2: Fs = 8.0kHz or Fvco = 2 x 2304 x 8kHz =36.864MHz, Fref = 2.304MHz.
Ndvsr = Integer [Fvco/Fref] = 16 = 10h;
Nrst= 1-1 = 0 from Fvco/Fref = 16/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example 3: Fs = 9.6kHz or Fvco = 2 x 2304 x 9.6kHz =44.2368MHz, Fref = 2.4576MHz.
Ndvsr = Integer [Fvco/Fref] = 18 = 16h;
Nrst= 1-1 = 0 from Fvco/Fref = 18/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
It is important to note that in general the NCO based feedback divider will generate a fixed jitter pattern
whose frequency components are at Fref/Accreset2 and its integer multiples. The overall jitter frequency
will be a nonlinear combination of jitters from both pre-scaler and PLL NCO. The fundamental frequency
component of this jitter is at Fref/Prst/Nrst. The PLL parameters should be selected to remove this jitter.
Three separate controls are provided to fine tune the PLL as shown in the following sections.
To ensure quick settling of PLL, a feature was designed into the 73M1903 where Ichp is kept at a higher
value until Lokdet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is
guaranteed to have the settling time of less than one Frame Synch period after a new set of NCO
parameters had been written to the appropriate registers. The serial port register writes for a particular
sample rate should be done in sequence starting from register 08h ending in register 0Dh. 0Dh register
should be the last one to be written to. This will be followed by a write to the next register in sequence
(0Eh) to force the transition of Sysclk from Xtal to Pllclk.
Upon the system reset, the system clock is reset to Fxtal/9. The system clock will remain at Fxtal/9 until
the Host forces the transition, but no sooner the second Frame Synch period after the write to 0Dh.
When this happens, the system clock will transition to PLLclk without any glitches thru a specially
designed deglitch MUX.
Examples of NCO settings
Example 1:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 13.714kHz(=2.4kHz x 10/7 x 4)
Step 1. First compute the required VCO frequency, Fvco, corresponding to
Fs = 2.4kHz x 10/7 x 4 = 13.714kHz, or
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 10/7 x 4 = 63.19543MHz.
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers.
This is initially given by :
MHz
Fxtal
Fvco
576
.
24
4
10/7
2.4kHz
2304
2
/
=
.
After a few rounds of simplification this ratio reduces to:
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相關代理商/技術參數 |
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|---|---|
| 73M1903-IM/F | 功能描述:電信線路管理 IC Modem AFE V.22Bis-V.92 RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-IM/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-IMR/F | 功能描述:電信線路管理 IC Modem AFE V.22Bis-V.92 RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-IMR/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-IVT/F | 功能描述:IC MODEM AFE V.22BIS 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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