
73M1903C
Modem Analog Front End
DATA SHEET
Page: 7 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
the data/control frames are 32 bits. The first 16 bits go to the first device; the next 16 bits go to the
second device in the chain, as timed by FSBD of the first device. For four daisy-chained devices, the
data/control frames are 64 bits. The first 16 bits go to the first device in the chain; the next 16 bits go to
the second device in the chain as started by FSBD of the first device, etc. FSBD is always a “Late Type”
frame sync.
Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of
the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the
1/4 of the data frame sync interval. In all cases involving slave and daisy-chain operation, only hardware
controlled Control Frames can be supported (Register 01h bit 0=1). Software requested control frames
are not allowed.
In slave mode the relationship of Fs and Fsclk is Fsclk/Fs, with a range of from 96 to 256 SCLKs per
FS.
Again, the host controls the relationship of
FS to SCLK, with the condition that Fsclk>750KHz and
Fsys=4608*Fs. The 79M1903C PLL must be programmed to generate Fsys with those conditions. To
program the 73M1903C NCOs, OSCIN (Fsclk)=SCLK=Fref when Pdvsr=1 and Prst=0 in the calculations.
Fsys in the previous discussion is Fvco in the calculations which is equal to 4608*Fs. For example, two
typical cases are Fsclk=256*Fs and Fsclk=144*Fs.
For the case when Fsclk=256*Fs and Fs=8KHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864MHz, and Sclk=256*8KHZ=2.048MHz. Therefore Ndvsr=36.864/2.048=18 (12h)
and Nrst=0
For the case when Fsclk=144*Fs an d Fs=8KHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864MHz and Sclk=144*8KHZ=1.152MHz. Therefore Ndvsr=36.864/1.152=32 (20h)
and Nrst=0
SERIAL DATA AND CONTROL
The bits transmitted on the SDOUT pin are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN
are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
In this case TX0=0 is forced.
If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN
input are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data
frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If