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參數資料
| 型號： | 73M1903C-IM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | LEAD FREE, QFN-32 |
| 文件頁數： | 44/45頁 |
| 文件大小： | 459K |
| 代理商： | 73M1903C-IM |
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73M1903C
Modem Analog Front End
DATA SHEET
Page: 8 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
CTL is high, a control frame will be initiated before the next data frame. A control frame allows the
controller to read or write status and control to the 73M1903C.
The control word received on the SDIN pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
The control word transmitted on the SDOUT pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
D7
D6
D5
D4
D3
D2
D1
D0
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received
on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is
set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data
contained in the register pointed to by address bits A6-A0. Only one control frame can occur between
any two data frames.
Writes to unimplemented registers are ignored. Reading an unimplemented register returns an unknown
value. The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is
set to a 0 the control frames occur mid way between data frames, i.e., the time between data frames is
equal. If SPOS is set to a 1, the control frame is of the way between consecutive data frames, i.e., the
control frame is closer to the first data frame. This is illustrated in Figure 4.
The TERIDIAN 73M1903C modem AFE IC includes a feature that shuts off the serial clock (SCLK) after
32 cycles of SCLK following the frame synch (figure 3). This mode is controlled by the SckMode pin. If
this pin is left open the clock will run continuously. If SckMode is set low, the clock will be gated on for 32
clocks for each
FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN
pin is sampled on the falling edge of SCLK. Figure 5 shows the timing diagrams for the serial port.
Figure 3: SCLK,
FS, and FSBD
SckMode=Low - SCLK Relative to
FS
SCLK
FS
32 Cycles of SCLK
SckMode=Low - Using FSBD for Daisy Chained
FS in Slave Mode
FSBD in Daisy
Chain mode
SCLK
32 Cycles of SCLK
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 73M1903C-IM/F | 功能描述:電信線路管理 IC Modem Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903C-IM/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903C-IMR/F | 功能描述:電信線路管理 IC Modem Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903C-IMR/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-EVM-600 | 功能描述:網絡開發工具 73M1903 w/Ppu & 600 Ohm Term-Usa & Japan RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數據速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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