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參數資料
| 型號： | 73S8009R-IMR |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC20 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, QFN-20 |
| 文件頁數： | 10/23頁 |
| 文件大小： | 342K |
| 代理商： | 73S8009R-IMR |
73S8009R Data Sheet
DS_8009R_056
18
Rev. 1.3
3.9
Chip Select
The CS pin is provided to allow multiple circuits to operate in parallel, driven from the same host control
bus. When CS is high, the pins RSTIN,
CMDVCC%, CMDVCC# and CLKIN control the chip as described.
The pins IOUC, AUX1UC, and AUX2UC operate to transfer data to the smart card via IO, AUX1, and
AUX2 when the smart card is activated. IO, AUX1, and AUX2 have 11 K
pull-up resistors while OFF
and RDY have 20 K
pull-up resistors.
When CS goes low, the states of the pins RSTIN,
CMDVCC%, CMDVCC#, and CLKIN are latched and
held internally. The pull-up for pins IOUC, AUX1UC, and AUX2UC become a very weak pull-up of
approximately 3 microamperes. No transfer of data is possible between IOUC, AUX1UC, AUX2UC and
the smart-card signals IO, AUX1, and AUX2. The signals
OFF and RDY are set to high impedance and
the internal 20 K
pull-up resistors are disconnected. PWRDN is not latched when CS is low.
The operation of the fault sensing circuits and card sense inputs (in regards to de-activation) are not
affected by CS.
CS
OFF, I/OUC, AUX1UC,
AUX2UC
CONTROL SIGNALS
FUNCTIONAL
HI-Z STATE
tSL
tDZ
tIS
tSI
tID
tDI
Figure 9: CS Timing Definitions
3.10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the
activation sequencer enables the I/O reception state. See Section 3.6 Activation and Deactivation
Sequence for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and
AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input
I/O line rising edge is detected, both I/O lines return to their neutral state.
Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or
output. The delay between the I/O signals is shown in Figure 11.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 73S8009R-IMR/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface IC RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8010C | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Smart Card Interface |
| 73S8010C-DB | 功能描述:界面開發工具 73S8010C Demo Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| 73S8010C-IL/F | 功能描述:I2C 接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| 73S8010C-ILR/F | 功能描述:I2C 接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
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