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參數資料
| 型號： | 74245 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 3-STATE Octal Bus Transceiver |
| 中文描述： | 三態八路總線收發器 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 66K |
| 代理商： | 74245 |
2000 Fairchild Semiconductor Corporation
DS006413
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS245
3-STATE Octal Bus Transceiver
General Description
These octal bus transceivers are designed for asynchro-
nous two-way communication between data buses. The
control function implementation minimizes external timing
requirements.
The device allows data transmission from the A Bus to the
B Bus or from the B Bus to the A Bus depending upon the
logic level at the direction control (DIR) input. The enable
input (G) can be used to disable the device so that the
buses are effectively isolated.
Features
I
Bi-Directional bus transceiver in a high-density 20-pin
package
I
3-STATE outputs drive bus lines directly
I
PNP inputs reduce DC loading on bus lines
I
Hysteresis at bus inputs improve noise margins
I
Typical propagation delay times, port-to-port 8 ns
I
Typical enable/disable times 17 ns
I
I
OL
(sink current)
24 mA
I
I
OH
(source current)
15 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
Order Number
DM74LS245WM
DM74LS245SJ
DM74LS245N
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Enable
G
Direction
Control
DIR
L
H
X
Operation
L
L
H
B Data to A Bus
A Data to B Bus
Isolation
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