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參數(shù)資料
| 型號： | 74283 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 4-Bit Binary Adder with Fast Carry |
| 中文描述： | 4位二進制加法器與快速卡里 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 158K |
| 代理商： | 74283 |
Switching Characteristics
at V
CC
e
5V and T
A
e
25
§
C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
R
L
e
2 k
X
Symbol
Parameter
C
L
e
15 pF
C
L
e
50 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time
Low to High Level Output
C0 to
R
1,
R
2
24
28
ns
t
PHL
Propagation Delay Time
High to Low Level Output
C0 to
R
1,
R
2
24
30
ns
t
PLH
Propagation Delay Time
Low to High Level Output
C0 to
R
3
24
28
ns
t
PHL
Propagation Delay Time
High to Low Level Output
C0 to
R
3
24
30
ns
t
PLH
Propagation Delay Time
Low to High Level Output
C0 to
R
4
24
28
ns
t
PHL
Propagation Delay Time
High to Low Level Output
C0 to
R
4
24
30
ns
t
PLH
Propagation Delay Time
Low to High Level Output
A
i
or B
i
to
R
i
24
28
ns
t
PHL
Propagation Delay Time
High to Low Level Output
A
i
or B
i
to
R
i
24
30
ns
t
PLH
Propagation Delay Time
Low to High Level Output
C0 to
C4
17
24
ns
t
PHL
Propagation Delay Time
High to Low Level Output
C0 to
C4
17
25
ns
t
PLH
Propagation Delay Time
Low to High Level Output
A
i
or B
i
to C4
17
24
ns
t
PHL
Propagation Delay Time
High to Low Level Output
A
i
or B
i
to C4
17
26
ns
Function Table
TL/F/6421–3
H
e
High Level, L
e
Low Level
Note:
Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs
R
1 and
R
2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
B4 are then used to determine outputs
R
3,
R
4, and C4.
3
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