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參數資料
| 型號： | 74ABT544PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 11/16頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR 3ST 8BIT INV 24TSSOP |
| 標準包裝： | 63 |
| 系列： | 74ABT |
| 邏輯類型： | 收發器，反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 輸出電流高，低： | 32mA，64mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 568-2487-5 935178850112 |
74ABT544
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
4 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
6.
Functional description
6.1 Function table
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
= LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for
each set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
Table 3.
Function selection[1]
Input
Output
Status
OEXX
EXX
LEXX
An or Bn
Bn or An
H
X
Z
disabled
XH
X
XZ
L
L
h
Z
disabled + latch
lZ
LL
h
L
latch + display
lH
L
H
L
transparent
LH
L
H
X
NC
hold
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74ABT544PW-T | 功能描述:總線收發器 OCTAL LATCHED XCVR INV 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ABT573 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs |
| 74ABT573_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs |
| 74ABT573_ZAF3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74ABT573_ZAF3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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