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參數資料
| 型號： | 74ABT544PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 14/16頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR 3ST 8BIT INV 24TSSOP |
| 標準包裝： | 2,500 |
| 系列： | 74ABT |
| 邏輯類型： | 收發器，反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 輸出電流高，低： | 32mA，64mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74ABT544PW-T 74ABT544PW-T-ND 935178850118 |
74ABT544
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
7 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
11. Waveforms
tPHL
HIGH to LOW
propagation delay
An to Bn or Bn to An; see Figure 5
2.4
3.6
4.5
2.4
5.2
ns
LEBA to An or LEAB to Bn; see Figure 6
3.0
4.4
5.3
3.0
6.2
ns
tPZH
OFF-state to HIGH
propagation delay
OEBA to An, OEAB to Bn; see Figure 7
1.8
3.0
3.9
1.8
4.7
ns
EBA to An, EAB to Bn; see Figure 7
1.9
3.4
4.1
1.9
5.0
ns
tPZL
OFF-state to LOW
propagation delay
OEBA to An, OEAB to Bn; see Figure 8
2.9
4.2
5.2
2.9
6.1
ns
EBA to An, EAB to Bn; see Figure 8
3.1
4.6
5.5
3.1
6.5
ns
tPHZ
HIGH to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 7
2.0
3.3
4.3
2.0
4.9
ns
EBA to An, EAB to Bn; see Figure 7
2.1
3.4
4.5
2.1
5.2
ns
tPLZ
LOW to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 8
2.0
2.8
5.8
2.0
6.3
ns
EBA to An, EAB to Bn; see Figure 8
2.0
3.0
6.2
2.0
6.7
ns
tsu(H)
set-up time HIGH
An to LEAB, Bn to LEBA; see Figure 9
3.0
1.5
-
3.0
-
ns
An to EAB, Bn to EBA; see Figure 9
3.0
1.5
-
3.0
-
ns
tsu(L)
set-up time LOW
An to LEAB, Bn to LEBA; see Figure 9
3.0
0.6
-
3.0
-
ns
An to EAB, Bn to EBA; see Figure 9
3.0
0.6
-
3.0
-
ns
th(H)
hold time HIGH
LEAB to An, LEBA to Bn; see Figure 9
+0.5
0.3
-
0.5
-
ns
EAB to An, EBA to Bn; see Figure 9
+0.5
0.2
-
0.5
-
ns
th(L)
hold time LOW
LEAB to An, LEBA to Bn; see Figure 9
+0.5
1.3
-
0.5
-
ns
EAB to An, EBA to Bn; see Figure 9
+0.5
1.3
-
0.5
-
ns
tWL
pulse width LOW
latch enable; see Figure 9
3.5
1.8
-
3.5
-
ns
Table 7.
Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter
Conditions
25
C; V
CC = 5.0 V
40 C to +85 C;
VCC = 5.0 V 0.5 V
Unit
Min
Typ
Max
Min
Max
VM =1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5.
Propagation delay input (An, Bn) to output (Bn, An)
001aac759
VOL
VOH
VM
tPHL
tPLH
VM
An, Bn
VI
GND
Bn, An
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相關代理商/技術參數 |
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| 74ABT544PW-T | 功能描述:總線收發器 OCTAL LATCHED XCVR INV 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ABT573 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs |
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