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參數資料
型號: 74ABT657DB,118
廠商: NXP Semiconductors
文件頁數: 1/17頁
文件大小: 0K
描述: IC TRANSCVR TRI-ST 8BIT 24SSOP
產品培訓模塊: Logic Packages
標準包裝: 1,000
系列: 74ABT
邏輯類型: 收發器,非反相
元件數: 1
每個元件的位元數: 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 24-SSOP
包裝: 帶卷 (TR)
其它名稱: 74ABT657DB-T
74ABT657DB-T-ND
935069180118
1.
General description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input
(pin T/R) determines the direction of the data ow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)
enables data from B ports to A ports.
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even
parity output, depending on the system. Pin PARITY is an output from the
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input
when receiving from port B to port A port (pin T/R = LOW).
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port
A is even, pin PARITY output goes LOW, keeping even parity.
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port
B is:
Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error
Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
2.
Features and benets
I Combinational functions in one package
I Low static and dynamic power dissipation with high speed and high output drive
I Output capability: +64 mA and 32 mA
I Power-up 3-state
I Latch-up protection exceeds 500 mA per JESD78B class II level A
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 — 15 March 2010
Product data sheet
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相關代理商/技術參數
參數描述
74ABT657DB-T 功能描述:總線收發器 OCTAL XCVR W/PARITY CHK 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABT657D-T 功能描述:總線收發器 OCTAL XCVR W/PARITY CHK 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABT657PW 功能描述:總線收發器 OCTAL XCVR W/PARITY CHK 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABT657PW,112 功能描述:總線收發器 OCTAL XCVR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ABT657PW,118 功能描述:總線收發器 OCTAL XCVR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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