
54AC11881, 74AC11881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SCAS390 – MARCH 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
Full Look-Ahead for High-Speed
Operations on Long Words
Arithmetic Operating Modes: Addition,
Subtraction, Shift Operand A One Position,
Magnitude Comparison, Plus Twelve Other
Arithmetic Operations
Logic Function Modes Exclusive-OR,
Comparator, AND, NAND, OR, NOR, Plus
Ten Other Logic Operations
Provides Status Register Checks
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
500-mA Typical Latch-Up Immunity at
125
°
C
Package Options Include Plastic “Small
Outline” Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
logic symbol
P
G
A=B
Cn+4
12
13
3
14
F0
4
F1
F2
F3
5
10
11
[8]
Q
P
B3
A3
19
25
[4]
[2]
[1]
Q
P
Q
P
Q
P
B2
A2
B1
A1
B0
A0
20
26
23
27
24
28
M
S3
S2
S1
S0
1
2
15
16
17
18
(0...15) CO
6(P=Q)
(0...15) CG
(0...15) CP
31
0
M
CI
4
0
ALU
Cn
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
Pin numbers shown are for DW, JT, and NT packages.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C
n
M
A=B
F0
F1
GND
GND
GND
GND
F2
F3
P
G
C
n+4
A0
A1
A2
A3
B0
B1
V
CC
V
CC
B2
B3
S0
S1
S2
S3
11881 . . . JT PACKAGE
11881 . . . DW OR NT PACKAGE
(T0P VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
S0
S1
S2
S3
C
n+4
G
P
A2
A1
A0
C
n
M
A=B
F0
4
26
14 15 16 1718
F
G
G
G
G
F
F
A
B
B
B
B
54AC11881 . . . FK PACKAGE
(TOP VIEW)
V
V
P