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參數資料
| 型號： | 74AC125B |
| 廠商： | 意法半導體 |
| 英文描述： | Octal D-type transparent latches 20-SSOP 0 to 70 |
| 中文描述： | 四總線緩沖器的三態 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 76K |
| 代理商： | 74AC125B |
74AC125
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
May 1997
PINCONNECTION AND IEC LOGICSYMBOLS
I
HIGH SPEED:t
PD
= 5 ns(TYP.) atV
CC
= 5V
I
LOWPOWER DISSIPATION:
I
CC
= 8
μ
A (MAX.) at T
A
=25
o
C
I
HIGH NOISEIMMUNITY:
V
NIH
=V
NIL
=28%V
CC
(MIN.)
I
50
TRANSMISSIONLINEDRIVING
CAPABILITY
I
SYMMETRICALOUTPUT IMPEDANCE:
|I
OH
| = I
OL
=24 mA (MIN)
I
BALANCED PROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto6V
I
PIN AND FUNCTION COMPATIBLEWITH
74SERIES125
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The AC125 is an high-speed CMOS QUAD BUS
BUFFERS fabricated with sub-micron silicon gate
and
double-layer
metal
technology. It is ideal for low power applications
maintaining high speed operation similar to
wiring
C
2
MOS
equivalentBipolar Schottky TTL.
These devices require the same 3-STATE control
input G to be taken high to make the output go in
to the high impedancestate.
All
inputs and
outputs
protectioncircuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
are
equipped with
ORDER CODES :
74AC125B
74AC125M
M
(Micro Package)
B
(Plastic Package)
1/8
相關PDF資料 |
PDF描述 |
|---|---|
| 74AC125M | Octal D-type transparent latches 20-SSOP 0 to 70 |
| 74AC125 | Octal D-type transparent latches 20-SSOP 0 to 70 |
| 74AC125 | QUAD BUFFER WITH 3-STATE OUTPUTS |
| 74AC125DCQB | CMOS Low Voltage 2.5 O Quad SPST Switch |
| 74AC125LCQR | Quad Buffer with TRI-STATE Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74AC125D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Buffer/Driver |
| 74AC125DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Buffer/Driver |
| 74AC125DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Buffer/Driver |
| 74AC125DCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad Buffer with TRI-STATE Outputs |
| 74AC125DCQR | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad Buffer with TRI-STATE Outputs |
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