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參數資料
| 型號： | 74AC163 |
| 廠商： | 意法半導體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous Presettable 4-Bit Counter(同步可預置的4位計數器) |
| 中文描述： | 同步可預置4位計數器（同步可預置的4位計數器） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 100K |
| 代理商： | 74AC163 |
74AC163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
December 1998
I
HIGHSPEED:
f
MAX
=200MHz(TYP.)atV
CC
=5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
50
TRANSMISSIONLINEDRIVING
CAPABILITY
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 24mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 6V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES163
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The
AC163
SYNCRONOUS
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL. It is a 4 bit binary counter with
SynchronousClear.
The circuits have four fundamental modes of
operation, in order of preference: synchronous
is
PRESETTABLE
a
high-speed
CMOS
COUNTERS
and
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine
the mode of operation as shown in the Truth
Table. A LOW signal on CLEAR overrides
counting and parallel loading and allows all
output to go LOW on the next rising
CLOCK. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
Qn inputs to be loaded into the flip-flops on the
next rising edge of CLOCK. With LOAD and
CLEAR, PE and TE permit counting when both
are HIGH. Conversely, a LOW signal on either
PE and TE inhibits counting.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
edge of
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
B
(Plastic Package)
ORDER CODES :
74AC163B
74AC163M
1/12
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