- 您現在的位置：買賣IC網 > PDF目錄369288 > 74AC16854 (Texas Instruments, Inc.) Dual 8-Bit To 9-Bit Parity Bus Transceivers.(雙8位-9位奇偶總線收發器) PDF資料下載
參數資料
| 型號： | 74AC16854 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual 8-Bit To 9-Bit Parity Bus Transceivers.(雙8位-9位奇偶總線收發器) |
| 中文描述： | 雙8位至9位奇偶校驗總線收發器。（雙8位-9位奇偶總線收發器） |
| 文件頁數： | 1/2頁 |
| 文件大小： | 20K |
| 代理商： | 74AC16854 |
54AC16854, 54ACT16854
74AC16854, 74ACT16854
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCAS410 – JUNE 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
PRODUCT PREVIEW information concerns products in
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
Members of Texas Instruments Widebus
Family
Packaged in Shrink Small-Outline 300-mil
Packages (SSOP) and 380-mil Fine-Pitch
Ceramic Flat Packages Using 25-mil
Center-to-Center Pin Spacings
Inputs are TTL- or CMOS-Voltage
Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
500-mA Typical Latch-Up Immunity at
125
°
C
description
The ’AC16854 and ’ACT16854 contain two
inverting 8-bit-to-9-bit parity bus transceivers. For
either transceiver, when data is transmitted from
the A bus to the B bus, an odd-parity bit is
generated and output on the parity I/O pin
(1PARITY or 2PARITY). When data is transmitted
from the B bus to the A bus, 1PARITY (or
2PARITY) is configured as an input and combined
with the B input data to generate an active-low
error flag if odd parity is not detected.
The error output (1ERR or 2ERR) is an
open-collector output. 1ERR (or 2ERR) can be
passed, sampled, stored, and cleared from the
latch using the latch enable (1EN and 2EN) and
clear (1CLR and 2CLR) inputs.
The 74AC16854 and 74ACT16854 are packaged in TI’s shrink small-outline package (SSOP) with 25-mil
center-to-center pin spacings. This package provides twice the I/O pin count and functionality of a standard
small-outline package in the same printed-circuit-board area.
The ’AC16854 has CMOS-compatible input thresholds. The ’ACT16854 has TTL-compatible input thresholds.
The 54AC16854 and 54ACT16854 are characterized over the full military temperature range of –55
°
C to 125
°
C.
The 74AC16854 and 74ACT16854 are characterized for operation from –40
°
C to 85
°
C.
EPIC and Widebus are trademarks of Texas Instruments
Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEB
1EN
1ERR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2ERR
2EN
2OEB
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
16854, 74ACT16854 . . . DL PACKAGE
16854, 54ACT16854 . . . WD PACKAGE
(T0P VIEW)
2OEA
P
相關PDF資料 |
PDF描述 |
|---|---|
| 74ACT16854 | Dual 8-Bit To 9-Bit Parity Bus Transceivers.(雙8位-9位奇偶總線收發器) |
| 74AC16862 | 20-Bit Bus Transceivers With 3-State Outputs(20位總線收發器(三態輸出)) |
| 74ACT16862 | 20-Bit Bus Transceivers With 3-State Outputs(20位總線收發器(三態輸出)) |
| 74AC16953 | 16-Bit Registered Bus Transceivers With 3-State Outputs(16位記錄總線收發器(三態輸出)) |
| 74ACT16953 | 16-Bit Registered Bus Transceivers With 3-State Outputs(16位記錄總線收發器(三態輸出)) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74AC16854DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 74AC16861DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 74AC16862DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 74AC16863DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 74AC16864DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
發布緊急采購，3分鐘左右您將得到回復。