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參數(shù)資料
| 型號： | 74ACT11161 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous Presettable 4-Bit Binary Counters(4位同步二進(jìn)制計數(shù)器) |
| 中文描述： | 同步可預(yù)置4位（4位同步二進(jìn)制計數(shù)器二進(jìn)制計數(shù)器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | 74ACT11161 |
54ACT11161, 74ACT11161
SYNCHRONOUS 4-BIT BINARY COUNTERS
SCAS382 – D3452, MARCH 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
Inputs are TTL-Voltage Compatible
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Fully Synchronous Operation for Counting
Synchronously Programmable
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
500-mA Typical Latch-Up Immunity at
125
°
C
Package Options Include Plastic
“Small-Outline” Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
This synchronous, presettable 4-bit binary
counter features an internal carry look-ahead for
application in high-speed counting designs.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable inputs and
internal gating.
This mode of operation eliminates the output counting spikes that are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of
the clock input waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and 5. As presetting is
synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with
the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the ’ACT11161 is synchronous and a low level at the clear input sets all four of the flip-flop
outputs low regardless of the levels of the clock, load, or enable inputs. This synchronous clear allows the count
length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output
of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output (RCO). RCO thus enabled will produce a high-level pulse while the count is 15 (HHHH). This
high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the
ENP or ENT are allowed regardless of the level of the clock input.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
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