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參數資料
| 型號： | 74AHC273PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/13頁 |
| 文件大小： | 0K |
| 描述： | IC OCT D FF POS-EDGE TRG 20TSSOP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 2,500 |
| 系列： | 74AHC |
| 功能： | 主復位 |
| 類型： | D 型總線 |
| 輸出類型： | 非反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 頻率 - 時鐘： | 50MHz |
| 延遲時間 - 傳輸： | 6ns |
| 觸發器類型： | 正邊沿 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
1.
General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ip-ops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ip-ops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the ip-op.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
2.
Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Ideal buffer for MOS microcontroller or memory
I Common clock and master reset
I Related product versions:
N 74AHC377; 74AHCT377 for clock enable version
N 74AHC373; 74AHCT373 for transparent latch version
N 74AHC374; 74AHCT374 for 3-state version
I Input levels:
N For 74AHC273: CMOS level
N For 74AHCT273: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specied from 40 °C to +85 °C and from 40 °C to +125 °C
74AHC273; 74AHCT273
Octal D-type ip-op with reset; positive-edge trigger
Rev. 03 — 13 May 2008
Product data sheet
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74AHC273PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Octal D-type flip-flop with reset; positive-edge trigger |
| 74AHC273PW-Q100J | 制造商:NXP Semiconductors 功能描述:74AHC273PW-Q100/TSSOP20/REEL13 制造商:NXP Semiconductors 功能描述:74AHC273PW-Q100/TSSOP20/REEL13 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC D-TYPE POS TRG SNGL 20TSSOP |
| 74AHC2G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-input OR gate |
| 74AHC2G00 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device |
| 74AHC2G00DC | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device |
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