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參數資料
型號: 74AHC74PW,112
廠商: NXP Semiconductors
文件頁數: 1/14頁
文件大?。?/td> 0K
描述: IC DUAL D F-F POS-EDGE 14TSSOP
產品培訓模塊: Logic Packages
標準包裝: 96
系列: 74AHC
功能: 設置(預設)和復位
類型: D 型
輸出類型: 差分
元件數: 2
每個元件的位元數: 1
頻率 - 時鐘: 75MHz
延遲時間 - 傳輸: 7.4ns
觸發器類型: 正邊沿
輸出電流高,低: 8mA,8mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 74AHC74PW
74AHC74PW-ND
935263079112
1.
General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type ip-op with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2.
Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC74: CMOS level
N For 74AHCT74: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specied from 40 °C to +85 °C and from 40 °C to +125 °C
74AHC74; 74AHCT74
Dual D-type ip-op with set and reset; positive-edge trigger
Rev. 05 — 9 June 2008
Product data sheet
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