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參數資料
| 型號： | 74ALVC162836DLRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 20位通用總線驅動器，三態輸出 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 153K |
| 代理商： | 74ALVC162836DLRG4 |
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Operates From 1.65 V to 3.6 V
Max t
pd
of 4 ns at 3.3 V
±
12-mA Output Drive at 3.3 V
Output Port Has Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
Designed to Comply With JEDEC 168-Pin and
200-Pin SDRAM Buffered DIMM Specification
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 20-bit universal bus driver is designed for 1.65-V
to 3.6-V V
CC
operation.
Data
flow
from
A
to
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
The output port includes equivalent 26-
series
resistors to reduce overshoot and undershoot.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
V
CC
Y17
Y18
GND
Y19
Y20
NC
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
V
CC
A17
A18
GND
A19
A20
LE
NC No internal connection
SN74ALVC162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES129E–MARCH 1998–REVISED OCTOBER 2004
Y
is
controlled
by
the
To ensure the high-impedance state during power up
or power down, OE should be tied to V
through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74ALVC162836DL
SN74ALVC162836DLR
SN74ALVC162836DGGR
SN74ALVC162836DGVR
TOP-SIDE MARKING
Tube
Tape and reel
Tape and reel
Tape and reel
SSOP - DL
ALVC162836
-40
°
C to 85
°
C
TSSOP - DGG
TVSOP - DGV
ALVC162836
VC2836
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1998–2004, Texas Instruments Incorporated
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74ALVC162838 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26з Series Resistors in the Outputs |
| 74ALVC162838T | 功能描述:寄存器 16-Bit Selectable Re RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74ALVC162838TX | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:BUFFER/FLIP-FLOP|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC |
| 74ALVC162839 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26з Series Resistors in the Outputs |
| 74ALVC162839T | 功能描述:寄存器 20-Bit Selectable Re RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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