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參數資料
| 型號： | 74ALVCH16373DGGE4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 中文描述： | 16位透明D型鎖存器三態輸出 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 489K |
| 代理商： | 74ALVCH16373DGGE4 |
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Operates From 1.65 V to 3.6 V
Max t
pd
of 3.6 ns at 3.3 V
±
24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
DGG OR DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020I–JULY 1995–REVISED NOVEMBER 2005
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither
load
nor
drive
the
buslines
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
significantly.
The
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1995–2005, Texas Instruments Incorporated
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相關代理商/技術參數 |
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|---|---|
| 74ALVCH16373DGGRG4 | 功能描述:閉鎖 16B Transp D-Type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373DG-T | 功能描述:閉鎖 3.3V 16-BIT D TRANS LATCH 3-S RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373DL | 功能描述:閉鎖 3.3V 16-BIT D TRANS LATCH 3-S RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373DL,112 | 功能描述:閉鎖 3.3V 16-BIT D TRANS RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373DL,118 | 功能描述:閉鎖 3.3V 16-BIT D TRANS RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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