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參數資料
型號: 74AUP1G97GS,132
廠商: NXP Semiconductors
文件頁數: 1/22頁
文件大小: 0K
描述: IC CONFIG MULT-FUNC GATE 6XSON
標準包裝: 5,000
系列: 74AUP
邏輯類型: 可配置多功能
電路數: 1
輸入數: 3
施密特觸發器輸入:
輸出類型: 單端
輸出電流高,低: 4mA,4mA
電源電壓: 0.8 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 6-XFDFN
供應商設備封裝: 6-XSON,SOT1202(1x1)
包裝: 帶卷 (TR)
其它名稱: 74AUP1G97GS132
1.
General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 Cto+85 C and 40 Cto+125 C
74AUP1G97
Low-power configurable multiple function gate
Rev. 8 — 15 August 2012
Product data sheet
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