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參數資料
型號: 74F283SJX
英文描述: Binary Adder
中文描述: 二進制加法器
文件頁數: 1/6頁
文件大小: 73K
代理商: 74F283SJX
2000 Fairchild Semiconductor Corporation
DS009512
www.fairchildsemi.com
April 1988
Revised September 2000
7
74F280
9-Bit Parity Generator/Checker
General Description
The F280 is a high-speed parity generator/checker that
accepts nine bits of input data and detects whether an
even or an odd number of these inputs is HIGH. If an even
number of inputs is HIGH, the Sum Even output is HIGH. If
an odd number is HIGH, the Sum Even output is LOW. The
Sum Odd output is the complement of the Sum Even out-
put.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
74F280SC
74F280SJ
74F280PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關PDF資料
PDF描述
74F280 9-bit odd/even parity generator/checker
74F280B 9-bit odd/even parity generator/checker(9位奇偶發生器/校驗器)
74F280PC 9-Bit Parity Generator/Checker
74F280SC 9-Bit Parity Generator/Checker
74F280SJ 9-Bit Parity Generator/Checker
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