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參數(shù)資料
型號: 74HC193D,652
廠商: NXP Semiconductors
文件頁數(shù): 1/30頁
文件大?。?/td> 0K
描述: IC COUNTER UP/DOWN SYNC 16SOIC
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 1,000
系列: 74HC
邏輯類型: 二進制計數(shù)器
方向: 上,下
元件數(shù): 1
每個元件的位元數(shù): 4
復(fù)位: 異步
計時: 同步
計數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
1.
General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behaviour. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
2.
Features and benefits
Input levels:
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 4 — 24 June 2013
Product data sheet
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參數(shù)描述
74HC193DB 功能描述:計數(shù)器 IC 4BIT BIN UP/DN CNTER SYNCHRONOUS RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
74HC193DB,112 功能描述:計數(shù)器 IC 4BIT BIN UP/DN CNTER RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
74HC193DB,118 功能描述:計數(shù)器移位寄存器 4-BIT BINARY UP/DOWN RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
74HC193DB-Q100J 制造商:NXP Semiconductors 功能描述:74HC193DB-Q100/SSOP16/REEL13// 制造商:NXP Semiconductors 功能描述:74HC193DB-Q100/SSOP16/REEL13// - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC COUNTER U/D 4BIT BIN 16SSOP
74HC193DB-T 功能描述:計數(shù)器 IC 4-BIT BINARY UP/DOWN COUNTER RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
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