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參數(shù)資料
| 型號(hào)： | 74HC643D-T |
| 英文描述： | 8-Bit Inverting/Non-Inverting Bus Trasceiver |
| 中文描述： | 8位反向/非反相總線Trasceiver |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 258K |
| 代理商： | 74HC643D-T |
M54/74HC620
M54/74HC623
October 1992
HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING
.
HIGH SPEED
t
PD
= 10 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH LS620/623
OCTAL BUS TRANSCEIVER
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
The M54/74HC620/623 are high speed CMOS
OCTALBUS TRANSCEIVERS fabricated in silicon
gate C
2
MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low powerconsumption.
Theseoctalbus transceivers aredesigned for asyn-
chronous two-way communication between data
buses. The control function implementation allows
maximum flexibility in timing.
These devices allow data transmission from the A
bus to Bbus or from the B to the A bus depending
upon the logic levels at the enable inputs (GBAand
GAB).The enable inputs can beused to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these devices
thecapability tostoredataby simultaneousenabling
of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus
lines(16 inall) will remain at their last states. The 8-
bit codes appearing on thetwo sets of buses will be
identical for the ’HC623 or complementary for the
’HC620. All inputs are equipped with protection cir-
cuits against static discharge and transient excess
voltage.
1/11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC646D | 功能描述:總線收發(fā)器 OCTAL TRANSCEIVER/ REGISTER 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74HC646D,652 | 功能描述:總線收發(fā)器 OCTAL TRANSCEIVER/ RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74HC646D,653 | 功能描述:總線收發(fā)器 OCTAL TRANSCEIVER/ RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74HC646DB | 功能描述:總線收發(fā)器 OCTAL TRANSCEIVER/ REGISTER 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74HC646DB,112 | 功能描述:總線收發(fā)器 OCTAL TRANSCEIVER/ RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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