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參數資料
| 型號： | 74HC74PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/21頁 |
| 文件大小： | 0K |
| 描述： | IC DUAL POS-EDG-TRG D FF 14TSSOP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 2,400 |
| 系列： | 74HC |
| 功能： | 設置（預設）和復位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數： | 2 |
| 每個元件的位元數： | 1 |
| 頻率 - 時鐘： | 82MHz |
| 延遲時間 - 傳輸： | 14ns |
| 觸發器類型： | 正邊沿 |
| 輸出電流高，低： | 5.2mA，5.2mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
1.
General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
2.
Features and benefits
Input levels:
For 74HC74: CMOS level
For 74HCT74: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 Cto+85 C and from 40 Cto+125 C
3.
Ordering information
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 4 — 27 August 2012
Product data sheet
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC74N
40 C to +125 C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT74N
74HC74D
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT74D
74HC74DB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT74DB
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