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參數資料
| 型號： | 74HCT4017N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JOHNSON DECADE COUNTER 16-DIP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 1,000 |
| 系列： | 74HCT |
| 邏輯類型： | 計數器，十進制 |
| 方向： | 上 |
| 元件數： | 1 |
| 每個元件的位元數： | 10 |
| 復位： | 異步 |
| 計數速率： | 67MHz |
| 觸發器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-DIP |
| 包裝： | 管件 |
1.
General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2.
Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4017: CMOS level
For 74HCT4017: TTL level
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 Cto+85 C and from 40 Cto+125 C
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 4 — 10 December 2013
Product data sheet
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