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參數資料
| 型號： | 74LCX112SJX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC FLIP FLOP DUAL JK NEG 16SOP |
| 標準包裝： | 2,000 |
| 系列： | 74LCX |
| 功能： | 設置（預設）和復位 |
| 類型： | JK 型 |
| 輸出類型： | 差分 |
| 元件數： | 2 |
| 每個元件的位元數： | 1 |
| 頻率 - 時鐘： | 150MHz |
| 延遲時間 - 傳輸： | 7ns |
| 觸發器類型： | 負邊沿 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
2001 Fairchild Semiconductor Corporation
DS012424
www.fairchildsemi.com
June 1998
Revised February 2001
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74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 7.5 ns tPD max (VCC = 3.3V), 10 A ICC max
s Power down high impedance inputs and outputs
s
±24 mA output drive (V
CC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model
> 2000V
Machine model
> 2000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LCX112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74LCX112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
J1, J2, K1, K2
Data Inputs
CP1, CP2
Clock Pulse Inputs (Active Falling Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
SD1, SD2
Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2
Outputs
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LCX11BQX | 功能描述:邏輯門 FINISHED GOOD RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LCX11BQX_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs |
| 74LCX11M | 功能描述:邏輯門 Trp 3-Input AND Gate RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LCX11M_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs |
| 74LCX11M_Q | 功能描述:邏輯門 Trp 3-Input AND Gate RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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