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參數資料
| 型號： | 74LCX16500MEA |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 18BIT UNIV BUS LV 56SSOP |
| 產品變化通告： | Die Material/Mold Compound Change 10/Sept/2008 |
| 標準包裝： | 25 |
| 系列： | 74LCX |
| 邏輯類型： | 通用總線收發器 |
| 電路數： | 18 位 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 56-SSOP |
| 包裝： | 管件 |
2002 Fairchild Semiconductor Corporation
DS012407
www.fairchildsemi.com
March 1995
Revised June 2002
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74LCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
5V Tolerant Inputs and Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16500 is designed for low voltage (2.5V or 3.3V)
VCC applications with the capability of interfacing to a 5V
signal environment.
The LCX16500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.0 ns tPD max (VCC = 3.3V), 20 A ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s
±24 mA output drive (V
CC = 3.0V)
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model
> 2000V
Machine model
> 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
74LCX16500G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LCX16500MEA
(Note 3)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX16500MTD
(Note 3)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
s Uses proprietary noise/EMI reduction circuitry
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相關代理商/技術參數 |
參數描述 |
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| 74LCX16500MEA_Q | 功能描述:總線收發器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MEAX | 功能描述:總線收發器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MTD | 功能描述:總線收發器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MTD_Q | 功能描述:總線收發器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LCX16500MTDX | 功能描述:總線收發器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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