參數資料
| 型號： | 74LCX540WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/14頁 |
| 文件大小： | 0K |
| 描述： | IC INVERTER 8-INPUT 20SOIC |
| 標準包裝： | 1,000 |
| 系列： | 74LCX |
| 邏輯類型： | 逆變器，緩沖器 |
| 電路數： | 1 |
| 輸入數： | 8 |
| 特點： | 三態 |
| 電源電壓： | 2 V ~ 3.6 V |
| 電流 - 靜態（最大值）： | 10µA |
| 輸出電流高，低： | 24mA，24mA |
| 邏輯電平 - 低： | 0.7 V ~ 0.8 V |
| 邏輯電平 - 高： | 1.7 V ~ 2 V |
| 額定電壓和最大 CL 時的最大傳播延遲： | 6.5ns @ 3.3V，50pF |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 20-SOIC |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
74LCX540
—
Lo
w
V
olta
g
e
Octal
Buff
er/Line
Driver
with
5V
T
olerant
Inputs
and
Outputs
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX540 Rev. 1.7.1
74LCX540
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
Features
■ 5V tolerant input and outputs
■ 2.3V–3.6V VCC specifications provided
■ 6.5ns tPD max. (VCC = 3.3V), 10A ICC max.
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal(1)
■
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance
– Human body model
> 2000V
– Machine model
> 200V
■ Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to VCC through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
General Description
The LCX540 is an octal buffer/line driver designed to be
employed as a memory and address driver, clock driver
and bus oriented transmitter/receiver.
This device is similar in function to the LCX240 while
providing flow-through architecture (inputs on opposite
side from outputs). This pinout arrangement makes this
device especially useful as an output port for micropro-
cessors, allowing ease of layout and greater PC board
density.
The LCX540 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V
signal environment. The LCX540 is fabricated with an
advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipa-
tion.
Ordering Information
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74LCX540WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX540SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX540BQX(2)
MLP20B
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
74LCX540MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX540MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Implements proprietary noise/ EMI reduction circuitry
December 2013
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