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參數資料
| 型號： | 74LCX543WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 2/8頁 |
| 文件大小： | 0K |
| 描述： | IC REGISTERED TXRX 8BIT 24SOIC |
| 標準包裝： | 1,000 |
| 系列： | 74LCX |
| 邏輯類型： | 寄存收發器，非反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
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2
74LCX543
Logic Symbols
IEEE/IEC
Data I/O Control Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Functional Description
The LCX543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A0–A7 or
take data from B0–B7, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Latch Status
Output Buffers
CEAB LEAB OEAB
H
X
Latched
High Z
X
H
X
Latched
—
L
X
Transparent
—
XX
H
—
High Z
LX
L
—
Driving
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| 74LCX573BQX | 功能描述:閉鎖 OCTAL TRANCEIVER(3V) RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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