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參數(shù)資料
| 型號(hào)： | 74LS373 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal D-type Transparent Latches(with three-state outputs) |
| 中文描述： | 八路D型透明鎖存器（帶三態(tài)輸出） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 89K |
| 代理商： | 74LS373 |
1/7
June 2003
I
HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A (MAX.) at T
A
= 25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
DESCRIPTION
The 74V2G02 is an advanced high-speed CMOS
DUAL 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
74V2G02
DUAL 2-INPUT NOR GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
74V2G02STR
SOT23-8L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LS373 | OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS |
| 74LS373 | LOW POWER SCHOTTKY |
| 74LS373 | OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT |
| 74V2G03STR | DUAL 2-INPUT OPEN DRAIN NAND GATE |
| 74V2G04 | TRIPLE INVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS373 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LS373DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
| 74LS373DW | 制造商:Texas Instruments 功能描述: |
| 74LS373DWMOT | 制造商:Motorola 功能描述:74LS373 |
| 74LS373NA | 制造商:North American Philips Discrete Products Div 功能描述:74LS373NA 制造商:NXP Semiconductors 功能描述:74LS373NA |
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