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參數(shù)資料
| 型號(hào)： | 74LVC161284TTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER |
| 中文描述： | 低壓高速IEEE1284收發(fā)器 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 217K |
| 代理商： | 74LVC161284TTR |
74LVC161284
5/11
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device
switching in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
V
CCcable
(V)
-40 to 85 °C
Min.
Max.
t
PLH
t
PHL
Propagation
Delay Time
A1-A8 to B1-B8,
A9-A13 to Y9-Y13
B1-B8 to A1-A8,
C14-C17 to A14-A17
PL
IN
to PL
OUT
HL
IN
to HL
OUT
DIR to A
HD to Bn, Y9-Y13
3.0
to
3.6
3.0
to
5.5
R
L
=500
C
L
=50pF
1
7.5
ns
R
L
=500
C
L
=50pF
1
9.0
ns
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
R
L
=500
C
L
=50pF
1
1
1
7.0
11.0
12
ns
ns
ns
t
PZH
t
PZL
Enable Delay
Time
3.0
to
3.6
3.0
to
5.5
1
8.5
ns
t
PLZ
t
PHZ
Disable Delay
Time
DIR to A
DIR to A
HD to Bn, Y9-Y13
3.0
to
3.6
3.0
to
5.5
1
1
1
8.5
8.5
8.5
ns
ns
ns
t
r
t
f
Rise and Fall Time
B1-B8, Y9-Y13 Open Drain
3.0
to
3.6
3.0
to
3.6
3.0
to
5.5
3.0
to
5.5
R
L
=500
C
L
=50pF
1
120
ns
t
OSLH
t
OSHL
Output To Output Skew Time (note1, 2)
R
PULL-UP
=500
C
L
=50pF
1
2
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
V
CC/CABLE
(V)
T
A
= 25 °C
Min.
Typ.
Max.
C
IN
Control Input Capacitance
(HD, DIR, A9-A13, C14-C17,
PL
IN
, HL
IN
)
I/O Pin Capacitance
Open
Open
4
pF
C
I/O
3.3
5.0
6
pF
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