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參數資料
| 型號： | 74LVC1G07 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Addressable Latches 16-SOIC -40 to 85 |
| 中文描述： | 16引腳小外形集成電路封裝，工作溫度-40℃到85℃的8位可尋址鎖存器 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 91K |
| 代理商： | 74LVC1G07 |
1.
General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2.
Features
I
Wide supply voltage range from 1.65 V to 5.5 V
I
5 V tolerant inputs for interfacing with 5 V logic
I
High noise immunity
I
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V).
I
±
24 mA output drive (V
CC
= 3.0 V)
I
ESD protection:
N
HBM EIA/JESD22-A114-B exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V.
I
CMOS low power consumption
I
Latch-up performance exceeds 250 mA
I
Direct interface with TTL levels
I
Inputs accept voltages up to 5 V
I
Multiple package options
I
Specified from
40
°
C to +85
°
C and
40
°
C to +125
°
C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004
Product data sheet
相關PDF資料 |
PDF描述 |
|---|---|
| 74LVC1G06 | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 74LVC1G04 | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 74LVC1G02 | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 74LVC1GU04 | Inverter |
| 74LVC1G86 | 2-input EXCLUSIVE-OR gate |
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| 74LVC1G07FW5-7 | 功能描述:Buffer, Non-Inverting 1 Element 1 Bit per Element Open Drain Output X1-DFN1010-6 制造商:diodes incorporated 系列:74LVC 包裝:剪切帶（CT） 零件狀態:有效 邏輯類型:緩沖器，非反向 元件數:1 每元件位數:1 輸入類型:- 輸出類型:開路漏極 電流 - 輸出高，低:-，32mA 電壓 - 電源:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:6-XFDFN 供應商器件封裝:X1-DFN1010-6 標準包裝:1 |
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