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參數資料
| 型號： | 74LVT16652ADL,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/21頁 |
| 文件大小： | 0K |
| 描述： | IC 16BIT BUS TXRX/REGIST 56SSOP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 26 |
| 系列： | 74LVT |
| 邏輯類型： | 寄存收發器，非反相 |
| 元件數： | 2 |
| 每個元件的位元數： | 8 |
| 輸出電流高，低： | 32mA，64mA |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 56-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 74LVT16652ADL 74LVT16652ADL-ND 935182500512 |
1.
General description
The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at
3.3 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.
Complimentary output enable (OEAB and OEBA) inputs are provided to control the
transceiver functions. Select control (SAB and SBA) inputs are provided to select whether
real-time or stored data is transferred. A LOW input level selects real-time data, and a
HIGH input level selects stored data. The circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data.
Data on the A or B bus, or both, can be stored in the internal ip-ops by LOW-to-HIGH
transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the
select control or output enable inputs. When SAB and SBA are in real-time transfer mode,
it is possible to store data without using the internal D-type ip-ops by simultaneously
enabling OEAB and OEBA. In this conguration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are at high- impedance, each set
of bus lines remains at its last level conguration.
2.
Features
s 16-bit bus interface
s 3-state buffers
s Output capability: +64 mA and
32 mA
s TTL input and output switching levels
s Input and output interface capability to systems at 5 V supply
s Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s Power-up reset
s Power-up 3-state
s No bus current loading when output is tied to 5 V bus
s Latch-up protection exceeds 500 mA per JESD78
s ESD protection:
x MIL STD 883 method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
74LVT16652A
3.3 V 16-bit bus transceiver/register; 3-state
Rev. 03 — 12 January 2005
Product data sheet
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| 74LVT16652ADL-T | 功能描述:總線收發器 3.3V 16-BIT BUS XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVT16835DGGRE4 | 功能描述:總線收發器 Replaced by SN74LVTH16835DGGR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVT16835DGGRG4 | 功能描述:總線收發器 UNIVERSAL BUS DRIVERS (UBDS) - 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVT16952DGGRG4 | 功能描述:總線收發器 3.3V ABT 16B Reg Xcvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVT18512DGGRE4 | 功能描述:特定功能邏輯 3.3V ABT Scan Test Device RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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