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參數資料
| 型號： | 74LVT573MTC |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC LATCH TRANSP OCT 3ST 20TSSOP |
| 標準包裝： | 73 |
| 系列： | 74LVT |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 獨立電路： | 1 |
| 延遲時間 - 傳輸： | 1.5ns |
| 輸出電流高，低： | 32mA，64mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 74LVT573MTC-ND 74LVT573MTCFS |
74L
VT573,
74L
VTH573
—
Lo
w
V
olta
g
e
Octal
T
ransparent
Latc
h
with
3-ST
A
TE
Outputs
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT573, 74LVTH573 Rev. 1.7.0
January 2008
74LVT573, 74LVTH573
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
■ Input and output interface capability to systems at
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH573),
also available without bushold feature (74LVT573)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink –32mA/+64mA
■ Functionally compatible with the 74 series 573
■ Latch-up performance exceeds 500mA
■ ESD performance:
– Human-body model
> 2000V
– Machine model
> 200V
– Charged-device model
> 1000V
General Description
The LVT573 and LVTH573 consist of eight latches
with 3-STATE outputs for bus organized system applica-
tions. The latches appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is low, the data
satisfying the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in the high
impedance state.
The LVTH573 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and
LVTH573 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74LVT573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVTH573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LVT573MTC | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74LVT CMOS SMD 74LVT573 |
| 74LVT573MTCX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT573PW | 功能描述:閉鎖 3.3V OCTAL D TRANS LATCH 3-S RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT573PW,112 | 功能描述:閉鎖 3.3V OCTAL D TRANS RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVT573PW,118 | 功能描述:閉鎖 3.3V OCTAL D TRANS RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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