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參數資料
| 型號： | 74LVTH162374MTX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 中文描述： | LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 472K |
| 代理商： | 74LVTH162374MTX |
www.ti.com
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
13
2
C1
1D
Pin numbers shown are for the DGG, DL, and WD packages.
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Recommended Operating Conditions
(1)
SN54LVTH162374, SN74LVTH162374
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS262L–JULY 1993–REVISED OCTOBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
4.6
UNIT
V
V
V
V
mA
mA
mA
mA
V
CC
V
I
V
O
V
O
I
O
I
O
I
IK
I
OK
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high state
(2)
Current into any output in the low state
Current into any output in the high state
(3)
Input clamp current
Output clamp current
7
7
V
CC
+ 0.5
30
30
–50
–50
70
63
42
36
150
V
I
< 0
V
O
< 0
DGG package
DL package
GQL/ZQL package
GRD/ZRD package
θ
JA
Package thermal impedance
(4)
°
C/W
T
stg
Storage temperature range
–65
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and V
> V
.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
(4)
SN54LVTH162374
MIN
2.7
2
SN74LVTH162374
MIN
2.7
2
UNIT
MAX
3.6
MAX
3.6
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
t/
v
t/
V
CC
T
A
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
V
V
V
V
0.8
5.5
–12
12
10
0.8
5.5
–12
12
10
mA
mA
ns/V
μ
s/V
°
C
Outputs enabled
200
–55
200
–40
125
85
(1)
All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
4
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