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參數資料
型號: 74V1T80STR
廠商: 意法半導體
英文描述: SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
中文描述: 單上升沿觸發的D -型觸發器
文件頁數: 1/9頁
文件大小: 123K
代理商: 74V1T80STR
1/9
April 2004
I
HIGH SPEED:
f
MAX
= 180MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
DESCRIPTION
The 74V1T80 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP
WITH
fabricated
with
sub-micron
double-layer metal wiring C
2
MOS technology. it is
designed to operate from 4.5V to 5.5V, making
this device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic inverted state that
was setup at the D input.
INVERTED
OUTPUT
gate
silicon
and
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
input and 0 to 7V can be accepted on input with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It’s available in the commercial temperature
range. All inputs and output are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V1T80
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-5L
SOT323-5L
74V1T80STR
74V1T80CTR
SOT323-5L
SOT23-5L
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