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參數(shù)資料
型號: 74VCX163245MTDX
廠商: Fairchild Semiconductor
文件頁數(shù): 1/12頁
文件大小: 0K
描述: IC TRANSCVR 16BIT N-INV 48TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Translator Solutions
標(biāo)準(zhǔn)包裝: 1
系列: 74VCX
邏輯功能: 變換器,3 態(tài)
位數(shù): 16
輸入類型: 電壓
輸出類型: 電壓
通道數(shù): 2
輸出/通道數(shù)目: 8
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4.4ns
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1212 (CN2011-ZH PDF)
其它名稱: 74VCX163245MTDXDKR
tm
74VCX163245
Lo
w
V
olta
g
e
16-Bit
Dual
Suppl
y
T
ranslating
T
ransceiver
with
3-ST
A
TE
Outputs
May 2007
2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VCX163245 Rev. 1.7
74VCX163245
Low Voltage 16-Bit Dual Supply Translating
Transceiver with 3-STATE Outputs
Features
Bidirectional interface between busses ranging from
1.65V to 3.6V
Supports Live Insertion and Withdrawal(1)
Static Drive (IOH/IOL)
– ±24mA @ 3.0V VCC
– ±18mA @ 2.3V VCC
– ±6mA @ 1.65V VCC
circuitry
Functionally compatible with 74 series 16245
Latchup performance exceeds 300mA
ESD performance:
– Human Body Model
>2000V
– Machine model
>200V
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note:
1. To ensure the high impedance state during power up
or power down, OEn should be tied to VCCB through a
pull up resistor. The minimum value of the resistor is
determined by the current sourcing capability of the
driver.
General Description
The VCX163245 is a dual supply, 16-bit translating
transceiver that is designed for 2 way asynchronous
communication between busses at different supply volt-
ages by providing true signal translation. The supply rails
consist of VCCA, which is a higher potential rail operating
at 2.3V to 3.6V and VCCB, which is the lower potential
rail operating at 1.65V to 2.7V. (VCCB must be less than
or equal to VCCA for proper device operation). This dual
supply design allows for translation from 1.8V to 2.5V
busses to busses at a higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direc-
tion of data flow. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable (OE)
input, when HIGH, disables both A and B Ports by plac-
ing them in a High-Z condition. The A Port interfaces
with the higher voltage bus (2.7V to 3.3V); The B Port
interfaces with the lower voltage bus (1.8V to 2.5V). Also
the VCX163245 is designed so that the control pins
(T/Rn, OEn) are supplied by VCCB.
The 74VCX163245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed oper-
ation while maintaining low CMOS power dissipation.
Ordering Information
Notes:
2. Ordering code “G” indicates Trays.
3. Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
74VCX163245G(2)(3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205,
5.5mm Wide
74VCX163245MTD(3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 6.1mm Wide
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
Uses proprietary Quiet Series noise/EMI reduction
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