- 您現在的位置：買賣IC網 > PDF目錄222840 > 74VHC112SJ (FAIRCHILD SEMICONDUCTOR CORP) Dual J-K Flip-Flops with Preset and Clear PDF資料下載
參數資料
| 型號： | 74VHC112SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 英文描述： | Dual J-K Flip-Flops with Preset and Clear |
| 中文描述： | AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 264K |
| 代理商： | 74VHC112SJ |
tm
74VHC112
Dual
J-K
Flip-Flops
with
Preset
and
Clear
May 2007
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC112 Rev. 1.2
74VHC112
Dual J-K Flip-Flops with Preset and Clear
Features
■ High speed: fMAX = 200MHz (Typ.) at VCC = 5.0V
■ Low power dissipation: ICC = 2A (Max.) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Pin and function compatible with 74HC112
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous
state changes are initiated by the falling edge of the
clock. Triggering occurs at a voltage level of the clock
and is not directly related to transition time. The J and K
inputs can change when the clock is in either state with-
out affecting the flip-flop, provided that they are in the
desired state during the recommended setup and hold
times relative to the falling edge of the clock. The LOW
signal on PR or CLR prevents clocking and forces Q and
Q HIGH, respectively. Simultaneous LOW signals on PR
and CLR force both Q and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Order Number
Package
Number
Package Description
74VHC112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
相關PDF資料 |
PDF描述 |
|---|---|
| 74VHC112N | Dual J-K Flip-Flops with Preset and Clear |
| 74VHC123AM | Dual Retriggerable Monostable Multivibrator |
| 74VHC123AMTC | Automotive Catalog Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 125 |
| 74VHC123AN | Dual Retriggerable Monostable Multivibrator |
| 74VHC123A | Automotive Catalog Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 125 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74VHC112SJ_Q | 功能描述:觸發器 Dual J-K Flip-Flops RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74VHC112SJX | 功能描述:觸發器 Dual J-K Flip-Flops RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74VHC123A | 制造商:Freescale Semiconductor 功能描述: |
| 74VHC123A_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Retriggerable Monostable Multivibrator |
| 74VHC123AFT | 功能描述:Monostable Multivibrator 9.6ns 16-TSSOP 制造商:toshiba semiconductor and storage 系列:汽車級，AEC-Q100，74VHC 包裝:剪切帶（CT） 零件狀態:停產 邏輯類型:單穩態 獨立電路:2 施密特觸發器輸入:無 傳播延遲:9.6ns 電流 - 輸出高，低:8mA，8mA 電壓 - 電源:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:16-TSSOP 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。