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參數資料
型號: 75C1406
廠商: Texas Instruments, Inc.
英文描述: TRIPLE LOW-POWER DRIVERS/RECEIVERS
中文描述: 三重低功率驅動器/接收器
文件頁數: 4/8頁
文件大小: 126K
代理商: 75C1406
SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148D – MAY 1990 – REVISED DECEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
DD
= 12 V, V
SS
= –12 V,
V
CC
= 5 V
±
10% (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High level output voltage
High-level output voltage
VIH = 0.8 V,
See Figure 1
RL = 3 k
,
VDD = 5 V,
VDD = 12 V,
VDD = 5 V,
VDD = 12 V,
VSS = –5 V
VSS = –12 V
VSS = –5 V
VSS = –12 V
4
4.5
V
10
10.8
VOL
Low-level output voltage
(see Note 3)
VIH = 2 V,
See Figure 1
RL = 3 k
,
–4.4
–4
V
–10.7
–10
IIH
IIL
High-level input current
VI = 5 V,
VI = 0,
See Figure 2
1
μ
A
Low-level input current
See Figure 2
–1
IOS(H)
High-level short-circuit
output current
VI = 0.8 V,
VO = 0 or VSS,
See Figure 1
–7.5
–12
–19.5
mA
IOS(L)
Low-level short-circuit
output current
VI = 2 V,
VO = 0 or VDD,
See Figure 1
7.5
12
19.5
mA
IDD
Supply current from VDD
No load,
All inputs at 2 V or 0.8 V
VDD = 5 V,
VDD = 12 V,
VDD = 5 V,
VDD = 12 V,
VO = –2 V to 2 V,
VSS = –5 V
VSS = –12 V
VSS = –5 V
VSS = –12 V
115
250
μ
A
115
250
ISS
Supply current from VSS
No load,
All inputs at 2 V or 0.8 V
–115
–250
μ
A
–115
–250
rO
Output resistance
VDD = VSS = VCC = 0,
See Note 4
300
400
All typical values are at TA = 25
°
C.
Not more than one output should be shorted at a time.
NOTES:
3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
4. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics at T
A
= 25
°
C, V
DD
= 12 V, V
SS
= –12 V, V
CC
= 5 V
±
10%
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
MAX
UNIT
μ
s
μ
s
μ
s
μ
s
tPLH
tPHL
tTLH
tTHL
Propagation delay time, low- to high-level output§
Propagation delay time, high- to low-level output§
Transition time, low- to high-level output
Transition time, high- to low-level output
3
RL
to 7 k
, CL
See Figure 3
2.5
3.5
,
0.53
2
3.2
0.53
2
3.2
tTLH
Transition time, low- to high-level output#
RL = 3 k
to 7 k
, CL = 2500 pF,
See Figure 3
1
2
μ
s
tTHL
Transition time, high- to low-level output#
RL = 3 k
to 7 k
, CL = 2500 pF,
See Figure 3
1
2
μ
s
SR
Output slew rate
RL = 3 k
to 7 k
, CL = 15 pF,
See Figure 3
4
10
30
V/
μ
s
§tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.
Measured between 10% and 90% points of output waveform
#Measured between 3-V and –3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
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