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參數資料
| 型號： | 75HVD05 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MS3420-10 |
| 中文描述： | 高輸出RS - 485收發 |
| 文件頁數： | 7/19頁 |
| 文件大小： | 220K |
| 代理商： | 75HVD05 |
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B
–
MAY 2002
–
REVISED MAY 2003
www.ti.com
7
PARAMETER MEASUREMENT INFORMATION
IOA
VOD
54
±
1%
0 or 3 V
VOA
VOB
IOB
DE
VCC
II
VI
A
B
Figure 1. Driver V
OD
Test Circuit
and Voltage and Current
Definitions
60
±
1%
VOD
0 or 3 V
_
+
–
7 V < V(test)
< 12 V
DE
VCC
A
B
D
375
±
1%
375
±
1%
Figure 2. Driver V
OD
With Common-Mode
Loading Test Circuit
VOC
27
±
1%
Input
A
B
VA
VB
VOC(PP)
VOC(SS)
VOC
27
±
1%
CL = 50 pF
±
20%
D
A
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50
CL Includes Fixture and
Instrumentation Capacitance
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
VOD
RL = 54
±
1%
50
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
tPLH
tPHL
1.5 V
1.5 V
3 V
≈
2 V
≈
–
2 V
90%
10%
0 V
VI
VOD
tr
tf
CL = 50 pF
±
20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VCC
VI
Input
Generator
90%
0 V
10%
0 V
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
RL = 110
±
1%
Input
Generator
50
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
3 V
S1
0.5 V
3 V
0 V
VOH
≈
0 V
tPHZ
tPZH(1 & 2)
1.5 V
1.5 V
VI
VO
CL = 50 pF
±
20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VO
VI
2.3 V
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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