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參數資料
| 型號： | 75V16F64GS16 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP) |
| 中文描述： | 64兆位閃存和16兆位偽靜態存儲器堆疊式多芯片封裝（MCP）技術 |
| 文件頁數： | 1/50頁 |
| 文件大小： | 255K |
| 代理商： | 75V16F64GS16 |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
1
75V16F64GS16
ISSI
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO
SRAM
STACKED MULTI-CHIP PACKAGE (MCP)
PRELIMINARY INFORMATION
AUGUST 2002
MCP FEATURES
Power supply voltage of 2.7 to 3.1 volt
High performance:
-
Flash access time as fast as 70 ns
- PSRAM access time as fast as 80 ns
Package: 65-Ball FBGA
Operating Temperature: –30°C to +85°C
FLASH MEMORY FEATURES
0.16 μm Process Technology
Simultaneous Read/Write Operations (Dual Bank)
FlexBank
TM
architecture
- Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Bank B : 24 Mbit (64 KB x 48)
- Bank C : 24 Mbit (64 KB x 48)
- Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Two virtual Banks are chosen from the combination
of four physical banks (Refer to "Example of Virtual
Banks Combination Table" and Simultaneous
Operation Table" in FLEXIBLE SECTOR-ERASE
ARCHITECTURE on FLASH MEMORY)
- Host system can program or erase in one bank, and
then read immediately and simultaneously from the
other bank with zero latency between read and write
operations.
- Read-while-erase
- Read-while-program
Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
- Sixteen 4 Kword and one hundred twenty-six 32
Kword sectors in word
- Any combination of sectors can be concurrently
erased
- Supports full chip erase
Hidden ROM (Hi-ROM) Region
- 256 byte of Hi-ROM, accessible through a new "HI-
ROM Enable" command sequence
- Factory serialized and protected to provide a secure
electronic serial number (ESN)
WP
/ACC Input Pin
- At V
IL
, allows protection of “outermost” 2
×
8 Kbytes
on both ends of boot sectors, regardless of sector
protection/unprotection status
- At V
IH
, allows removal of boot sector protection
- At V
ACC
, program time will be reduced by 40 %
Embedded Erase
TM
Algorithms
- Automatically preprograms and erases the chip
or any sector
Embedded Program
TM
Algorithms
- Automatically writes and verifies data at specified
address
Data Polling and Toggle Bit Feature for Detection of
Program or Erase Cycle Completion
Ready/Busy Output (RY/
BY
)
- Hardware method for detection of program or
erase cycle completion
Automatic Sleep Mode
- When addresses remain stable, the device
automatically switches itself to low power mode.
Low V
CC
f Write Inhibit
≤
2.5 V
Program Suspend/Resume
- Suspends the program operation to allow a read
in another byte
Erase Suspend/Resume
- Suspends the erase operation to allow a read
data and/or program in another sector within the
same device
PSRAM FEATURES
Power Dissipation:
- Operating : 20 mA Max
- Standby : 70 μA Max
- Power Down
Power down Control by CE2r
Byte Write Control :
LB
(DQ
7
-DQ
0
),
UB
(DQ
15
-DQ
8
)
4 words Address Access Capability
: 10 μA Max
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