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參數資料
| 型號： | 7805ALPRPFK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Latchup Protected ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 封裝： | DFP-28 |
| 文件頁數： | 7/18頁 |
| 文件大小： | 262K |
| 代理商： | 7805ALPRPFK |
M
7
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
01.10.05 Rev 9
BUSY delay after data valid
t
10
t
11
t
12
t
13
t
14
9, 10, 11
50
200
--
ns
Previous data valid delay after R/C low
9, 10, 11
--
7.4
--
μs
R/C to CS setup time
9, 10, 11
10
--
--
ns
Time between conversions
9, 10, 11
10
--
--
μs
Bus access time
9, 10, 11
10
--
83
ns
1. Tested by application of signal.
T
ABLE
16. 7805ALP C
ONTROL
L
INE
F
UNCTION
FOR
R
EAD
AND
C
ONVERT
CS
R/C
BUSY
O
PERATION
1
X
X
None. Databus is in Hi-Z state.
"
0
1
Initiates conversion "n". Databus remains in Hi-Z state.
0
"
1
Initiates conversion "n". Databus enters Hi-Z state.
0
1
Conversion "n" completed. Valid data fromconversion "n" on the databus.
"
1
1
Enables databus with valid data fromconversion "n".
"
1
0
Enables databus with valid data fromconversion "n-1". Conversion "n" in progress.
0
0
Enables databus with valid data fromconversion "n-1". Conversion "n" in
progress."
New conversion initiated without acquisition of a new signal. Data will be invalid.
CS and/or R/C must be HIGH when BUSY goes HIGH.
New convert commands ignored. Conversion "n" in progress.
0
0
X
X
0
T
ABLE
15. 7805ALP C
ONVERSION
T
IMING1
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
D
ESCRIPTION
S
YMBOL
S
UBGROUPS
M
IN
T
YP
M
AX
U
NIT
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